1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a plastic-packaged semiconductor device in which the main surfaces of a plurality of chips are connected to leads while being arranged so as to oppose one another.
2. Background Art
A plastic-packaged semiconductor device having two chips encapsulated therein is disclosed in, e.g., (1) Japanese Patent Application Laid-open No. Hei-7-130949, (2) Japanese Patent Application Laid-open No. Hei-4-61152, and (3) Japanese Patent Application Laid-open No. Hei-5-109975.
Publication (1) describes a semiconductor device having two chips encapsulated therein such that their main surfaces are arranged so as to oppose each other with a lead sandwiched therebetween and such that each of the main surfaces faces the corresponding side of the lead. Electrode pads are provided on the respective surfaces of the chips in a symmetrical pattern. The electrode pads facing each other are connected to a common lead with electrode bumps disposed between the respective pads and the lead. As can be seen from FIG. 2 of Publication (1), in order to enable selection of one of the chips, the two chips additionally required a total of six electrode pads, six electrode bumps, and two lead frames. Further, there must be separately prepared chips having electrode pads arranged thereon in different patterns, thus deteriorating the mass-productivity of the semiconductor device.
Publication (2) describes a semiconductor device having two chips encapsulated therein such that their main surfaces are arranged so as to oppose each other with a lead sandwiched therebetween and such that each of the main surface faces the corresponding side of the lead. Electrode pads are provided on the respective main surfaces of the chips in a symmetrical pattern while a common lead is sandwiched therebetween. A signal other than a chip selection signal is input to a pair of electrode pads as a common signal. Another pair of electrode pads are provided on the respective main surfaces in an asymmetrical pattern, and one of the electrode pads is connected to a lead specifically provided for one chip, and the other electrode pad is connected to a lead specifically provided for the other chip. Only the chip selection signal is input to the electrode pad of the chip to be selected. As can be seen from FIG. 2 of Publication (2), to enable selection of one of the chips, a dummy pad not connected to an internal circuit of the chip must be additionally provided on each chip, and there must be separately prepared chips having electrode pads arranged in different patterns.
Publication (3) describes a semiconductor device comprising two chips. Electrode pads are provided in the center of the main surface of each chip and are arranged along the longitudinal direction. The chips are encapsulated in a package in such a way that the main surfaces of the chips are oriented in the same direction. The corresponding electrode pads provided on the chips are connected to a common lead by means of a wire, thus rendering a manufacturing process complicated. As shown in FIGS. 6 and 8 of Publication (3), two lead frames are required, adding to the manufacturing cost.
The present invention has been conceived to solve such drawbacks as mentioned previously, and a first object of the present invention is to provide a plastic-packaged semiconductor device which has improved mass-productivity and enables selection of one of a plurality of chips with a fewer number of leads, wherein the main surfaces of the chips are connected to leads and are arranged so as to face one another.
A second object of the present invention is to provide a plastic-packaged semiconductor device which comprises two chips having electrode pads provided thereon in an identical pattern and having their main surfaces arranged so as to oppose each other and which enables selection of one of the two chips through use of one lead frame.
A third object of the present invention is to provide a plastic-packaged semiconductor device which comprises two chips having electrode pads provided thereon in a symmetrical pattern and having their main surfaces arranged so as to oppose each other and which enables selection of one of the chips through use of one lead frame.
According to one aspect of the present invention, a plastic-packaged semiconductor device comprises at least a pair of chips, and the pair of chips are positioned so as to face each other and connected to common leads between the pair of chips.
The pair of chips include a plurality of electrode pads which are provided respectively in mutually corresponding positions on the main surface of the respective chips such that the electrode pads provided in the corresponding positions form a plurality of pairs of electrode pads between the pair of chips.
A plurality of pairs of electrode pads are electrically connected respectively to opposite sides of one of the common leads by way of electrode bumps formed on each of the respective electrode pads, and permit input or output of a common signal in or from the chips.
Further, a pair of electrode pads are provided side by side to each other between the pair of chips. One of the pads is electrically connected to one side of a selected common lead by way of an electrode bump formed on the electrode pad, and the other of the pads is electrically connected to other side of the selected common lead by way of an electrode bump formed on the electrode pad. The pair of electrode pads permit input or output of individual signals to the respective chips.
According to another aspect of the invention, a pair of electrode pads are provided mutually at selected positions between the pair of chips. One of the pads is electrically connected to a first selected lead by way of an electrode bump formed on the electrode pad, and the other of the pads is electrically connected to a second selected lead by way of an electrode bump formed on the electrode pad. The pair of electrode pads permit input or output of individual signals to the respective chips.
In another aspect, in the semiconductor device, the pair of pads are arranged in a row substantially along the center line of the main surface of the respective chips.
In another aspect, in the semiconductor device, the pair of pads are arranged in two rows on the main surface of the respective chips in a longitudinal direction.
In another aspect, in the semiconductor device, a plurality of electrode pads are provided on the main surface of the respective chips in a symmetrical manner such that the electrode pads provided in corresponding positions form a pair of electrode pads.
In another aspect, in the semiconductor device, each of the pair of chips works as a composite chip which incorporates therein a plurality of unit chips.
In another aspect, in the semiconductor device, the electrode pads are formed into a row substantially along the center line of the main surface of the chips and are electrically connected to the leads, and the lead are fixedly bonded to the main surfaces of the chips by means of a resin-made adhesive.
Other and further objects, features and advantages of the invention will appear more fully from the following description. dr
FIGS. 1A to 1D are cross-sectional views arranged in sequential order of manufacture of a semiconductor device according to first and second embodiments of the present invention;
FIGS. 2A and 2B are plan views for describing the layout of electrode pads according to the first and second embodiments;
FIG. 3 is a plan view for describing connection between leads and electrode bumps according to the first embodiment;
FIGS. 4A and 4B are cross-sectional views for explaining connection among electrode pads, electrode bumps, individual leads, and common leads according to the first, second, and fourth embodiments;
FIG. 5 is a plan view for describing connection between leads and electrode bumps according to the second embodiment;
FIG. 6 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention;
FIGS. 7A and 7B are plan views for describing the layout of electrode pads according to the third embodiment;
FIG. 8 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention;
FIGS. 9A and 9B are plan views for describing the layout of electrode pads according to the fourth embodiment; and
FIG. 10 is a plan view for describing connection between electrode bumps and leads according to the fourth embodiment.